Embodiments of the inventive concept relate generally to semiconductor memory devices. More particularly, embodiments of the inventive concept relate to semiconductor memory devices capable of adjusting a charge sharing time required to share charge between a cell capacitor and a bitline.
Various semiconductor devices, such as dynamic random access memories (DRAMs), store data in cell capacitors and read the data through bitlines connected to the cell capacitors. Because the cell capacitors in modern semiconductor devices tend to be relatively small and store relatively small amounts of charge, parasitic capacitances on the bitlines and other elements such as sense amplifiers can have a significant effect on the timing required to transfer the charges from the cell capacitors to other elements. In general, a cell capacitor must be connected to a bitline for a charge sharing time sufficient to account for the parasitic capacitances. For instance, to ensure an adequate sensing margin for a sense amplifier, a cell capacitor must be connected to a bitline long enough to transfer charges to the sense amplifier in the presence of parasitic capacitances. To ensure an adequate charge sharing time, semiconductor memory devices commonly include a delay circuit to control the timing of read operations.
Such delay circuits may be implemented, for instance, by a combination of gates or a resistor-capacitor (RC) delay circuit. RC delay circuits can be adjusted to provide different amounts of delay using adjustment elements such as fuses.